Just a quick entry today. Recently, I was hacking on a PXA3xx NAND flash support for OpenOCD. It's finally ready, though it has a few limitations. The preliminary version is available in the
OpenPXA GIT as always, though the patches are being pushed into mainline OpenOCD. The limitations mentioned before are that you can't erase multiple blocks as once, you have to do it one after another for now. Also, this driver for now works only for large block devices, but adding support for small block ones should be easy. And the driver is quite slow too, so it's probably only useful for flashing in the bootloader.
A quick howto on reflashing the bootloader using the NAND code in OpenOCD follows:
- run OpenOCD with the following command: openocd -s tcl -f board/colibri_pxa320.cfg -f interface/jtagkey.cfg (for Colibri/PXA3xx board and Amontec JTAGkey)
- connect to OpenOCD using telnet: telnet localhost 4444
- Issue the following commands, one after another:
- reset halt
- nand probe 0
- nand erase 0 0x0 0x20000 ; nand erase 0x20000 0x20000 (erase first two blocks)
- nand write 0 bootloader.img 0x0
- To read data from NAND, use: nand dump 0 dump.img 0x0 0x800 (0x0 is base address, 0x800 is amount of bytes)
6 comments:
Hi Marex. I successfully flash you version of u-boot into my colibri_pxa320. But after some playing i build slightly modified version of u-boot and flash it. After reboot board totally hangs. And now i can`t reflash u-boot - openocd have some kind of trouble in communication with cpu:
Open On-Chip Debugger
> reset halt
JTAG tap: colibri_pxa320.cpu tap/device found: 0x6e642013 (mfg: 0x009, part: 0xe642, ver: 0x6)
Bad value '00' captured during DR or IR scan:
check_value: 0x02
check_mask: 0x07
JTAG error while writing DCSR
Bad value '00' captured during DR or IR scan:
check_value: 0x02
check_mask: 0x07
JTAG error while writing DCSR
Bad value '00' captured during DR or IR scan:
check_value: 0x02
check_mask: 0x07
JTAG error while writing DCSR
Bad value '00' captured during DR or IR scan:
check_value: 0x02
check_mask: 0x07
JTAG error while writing DCSR
Bad value '00' captured during DR or IR scan:
check_value: 0x02
check_mask: 0x06
JTAG error while reading TX
error while polling TX register, reset CPU
target state: halted
target halted in ARM state due to undefined, current mode: User
cpsr: 0x00000000 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
so i cannot halt cpu =( Do you have any suggestions? I use Olimex arm-usb-ocd adapter.
With best regards, Urx
^ Same problem here...
I think this OpenPXA GIT work very fast, i really love it. this program is similar when i go to buy viagra for my boyfriend. that really worked like this Linux program
Hi Marex,
I was very happy to find your website and the work you did. Thank you for your contribution.
I tried to load bootloader on a PXA320 C0 via openocd with no success.
It fails already on the first reset halt in a similar way as Yuri described.
Could you comment why would halt fail?
Is this a cable issue?
Thank you very much for your comment.
I use for my experiment the Amontek Jtag key tiny and the PXA3xx patches from your master git commit. I got openocd as you suggest via:
git clone git://repo.or.cz/openocd.git
Thank you very much for your help and keep the good work!
All the best,
Plamen
Hi Marex,
I also have similar problem, as Yuri shown.
Could you write me which OpenOCD version do you base on?
Best regards,
Marcin
Try to set more big delay, for example "jtag_nsrst_delay 3000" and also try to set "reset_config trst_push_pull srst_push_pull". This two options helps me to halt my pxa310.
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